| Today, the bandwidth between DRAM and logic modules becomes the bottleneck to improvement of system performance, especially for high performance data processing units, such as digital signal processing (DSP) module and graphic processors. Although embedded DRAM (eDRAM) is a solution, its low yield and high design complexity prevents it being widely adopted by IC designers. An alternative is area-IO DRAM. Area-IO makes it possible to extend the IO width to hundreds of bits and System-in-a-Package (SiP), a generalization of System-on-a-Chip (SoC), provides a cost-effective platform for large-scale DRAM and logic integration without the limitation to the number of package pins. SiP overcomes formidable integration barriers without compromising individually optimized chip technologies, such as DRAM processing technology and ASIC processing technology. By preserving on-chip electrical environment, area-IO DRAM/Logic integration with SiP matches or exceeds embedded DRAM. This thesis presents a comprehensive analysis of an area-IO DRAM design, including architecture design and an innovative configurable interface module for area-IO DRAM/Logic integration, which enables one generic area-IO DRAM to meet the IO width requirements of different applications. A DRAM power model and an IO power model for the system-level analysis of area-IO DRAM/Logic integration have been developed and verified. Chip-package co-analysis for timing and power in flip-chip design flow, which is part of SiP platform development for area-IO/Logic integration, is also covered in this thesis. |
