High-speed VLSI architectures for error-correcting codes and cryptosystems

This thesis focuses on the design of high-speed VLSI architectures for the Advanced Encryption Standard (AES) algorithm, long Bose-Chaudhuri-Hocquenghem (BCH) encoders and soft-decision Reed-Solomon (RS) decoding.; The AES became the new U.S. government standard in 2000. A novel high-speed architecture for the hardware implementation of the AES algorithm is presented in this thesis. The proposed design employs combinational logic only, such that the advantage of sub-pipelining can be further exploited. In addition, composite field arithmetic is employed in appropriate transformations of the AES algorithm to reduce area, and the inversion in subfield GF(24) is carried out by an efficient approach. Furthermore, the construction of optimum composite fields for the AES algorithm is provided. Implemented on a Xilinx FPGA device, the proposed architecture can achieve a throughput of 21.56Gbps.; Long BCH codes can achieve around 0.6dB additional coding gain over RS codes in optical communication systems. The fanout bottleneck in the linear feedback shift register (LFSR)-based parallel long BCH encoders can be eliminated by introducing a second LFSR architecture. However, the speedup of parallel processing is offset by the long clock period imposed by the feedback loops in the introduced LFSR. In this thesis, three novel schemes are proposed to replace the second LFSR with feedback-free architectures. For a 32-parallel (8191, 7684) BCH code, the proposed architectures can achieve more than 100% speedup over prior efforts.; The recently developed Koetter-Vardy (KV) soft-decision decoding algorithm of RS codes can achieve substantial coding gain for high-rate codes. A novel architecture based on root-order prediction is presented in this thesis to speed up the factorization step of the KV algorithm. As a result, the exhaustive-search-based root computation from the second iteration of the factorization step is circumvented with more than 99% probability. In addition, resource sharing among root-prediction blocks, as well as normal basis representation for finite field elements and composite field arithmetic, are exploited to reduce the silicon area significantly. Applying the proposed architecture to a typical (255, 239) RS code, a speedup of 141% can be achieved over the fastest prior effort, while the area consumption is reduced to 31%.