High-speed Oqpsk Digital Demodulator Synchronization Algorithm And Parallel Architecture To Achieve

High date-rate OQPSK (Offset Quadrature Phase Shift Keying) digital transmission, which has the advantage of high date rate, good spectrum efficiency and non-linearity resistance, compactness, and stability, adapts to the trend of global communication and the rapid growing demand for wireless multimedia communication service with long distance. It is applied broadly in satellite communication system and wide-band mobile communication system. Therefore, research about high data-rate OQPSK digital demodulation technology has important value in application.Carrier and timing synchronizations are the key process of demodulation. OQPSK modulation has a delay by half of the symbol period on the quadrature rail, which causes its synchronization scheme more difficult than conventional QPSK. There are many synchronization algorithms for OQPSK known today. But these algorithms hardly work stably and desirably under the practical condition that the SNR of received signal is very low caused by the energy constraint for mobile equipment and the long transmission distance. Furthermore, because the received modulation signal with high data rate is wide-band signal, the non-linear group delays of channel or front-end analogy filters are bad influences on synchronization and decision, reducing the performance heavily. Moreover, the date rate of digital demodulation is usually limited by the speed of digital components. To solve above problem, work of this thesis shown as follow have been done:1. Synchronization algorithms for the digital receiver known today, including carrier frequency synchronization, carrier phase synchronization and timing synchronization, are investigated broadly. Via theoretical analysis, simulation, performance compare, selection, integration, and amelioration, synchronization scheme, in which the synchronization system parameters are regulated by synchronization estimators, is proposed this thesis. It is shown that this scheme works well when the SNR of received signal is very low (as low as -2dB).2. The influence of the non-linear group delays of channel or front-end analogy filters on performances of synchronization and demodulation with high date-rate wide-band modulation signal is investigated. A digital pre-filter as the equalizer is designed to solve the problem.3. The methods of design and implement of parallel high speed digital signal processing structure are investigated. By converting synchronization and demodulation scheme into parallel structure, 480Mbps high date-rate demodulator is realized at the expense of increased hardware resource.4. This thesis validates the efficacy of the synchronization scheme and the realizable of the parallel structure, by Matlab / Simulink simulations, including theoretical simulation, simulation of parallel structure, and fixed-point simulation. This thesis also optimizes the algorithms, structure, and adjusts the parameters, based on demand of the application.5. This thesis implements the high data-rate OQPSK digital parallel demodulator by FPGA. The main works are the VHDL design and simulation of the parallel synchronization and demodulation modules and the whole. Using the Xilinx FPGA evaluation kit based on XC4VLX25, the modules are debugged.The results of the research indicate that the synchronization and demodulation scheme and parallel structure proposed in this thesis satisfy the demand of the high date-rate OQPSK digital transmission system design.