Modeling and description of embedded processors for the development of software tools

Increasing design and manufacturing costs are prompting a shift in electronic design from hardwired application-specific integrated circuits (ASICs) to the use of software on programmable platforms. In order to minimize the power and performance overhead of such platforms, domain or application-specific processors have been used. The development of such processors requires not only traditional electronic design automation tools but also processor-specific software tools such as compilers and instruction set simulators. In early development stages when multiple processor design points are explored, it is necessary to have the software tools synthesized from high level processor descriptions. This dissertation presents an approach that aims to automate the synthesis of these software tools. The foundation of the approach is a novel concurrency model, the operation state machine (OSM). The OSM model views a processor in two interacting levels: the operation level where instruction behavior is represented and the hardware level where resources required for instruction execution are managed. Through proper abstraction, the model significantly simplifies the specification of concurrency and control semantics without compromising flexibility. This dissertation then presents the MESCAL Architecture Description Language (MADL) which is designed using the OSM model. It describes the major design considerations of MADL and the synthesis of software tools including cycle-accurate simulators, instruction set simulators, disassemblers, and binary decoders from MADL-based processor models. It further goes on to show how this description can be used to extract reservation tables for use in instruction schedulers in compilers. Experimental results show that the MADL-based approach is very effective in supporting these software tools and the synthesized cycle-accurate simulators have competitive simulation speeds compared to their hand-coded counterparts.