10 GHz LC VCOs for high-speed serial data communication ICs

As both wireless and optical communications systems move towards high-data-rate applications, high-frequency low-phase-noise oscillators are important building blocks in the transmit and receive channels. With scaling, CMOS technology proves to be a viable option for designing low power and low cost front-end circuitry for high-speed optical communication systems.; This thesis presents the design methodology and implementation of monolithic GHz range voltage controlled oscillators for high-speed serial data communication ICs in submicron CMOS technology. The design methodology illustrated, provides an efficient and practical approach by using a simulator-based design strategy with appropriate reference to the existing VCO noise model and theory. There are three LC VCO presented in this thesis. The first (fo = 2GHz) and the second (fo = 10GHz) oscillators use a complementary negative transconductance topology while the third oscillator (fo = 10GHz) works on self-switched inductor concept. On-chip broadband and high Q inductors are designed and optimized using dedicated software and 2.5D electromagnetic simulator. The design of PN-junction based and an "accumulation-mode" MOS tuning varactors are presented. Practical issues pertaining to CMOS LC VCO design, layout and testing are also discussed. The characterization of the VCO and the integrated passive components are presented. Best performance is achieved for the second VCO with phase noise of -100dBc/Hz at 1 MHz offset from a center frequency of 10.24GHz. The tuning range is 860MHz. The circuit consumes 2.4mA form a 1.2V supply and has met the SONET OC192 jitter/phase noise requirement with fair margin of 10dBc. The comparison of designed LC VCOs with the recent literature shows significant improvement with respect to phase noise and power consumption. Finally, several recommendations for further improvement in VCO performance and issues need to be addressed in future work are discussed.