| Orthogonal frequency division multiplexing (OFDM) modulation is of considerable interest for broadband wireless networking, such as 5GHz 802.11a wireless local area network (WLAN) in US or high performance radio local area network (HIPERLAN) in Europe. One of the major drawbacks of this modulation technique is its vulnerability to RF local oscillator (LO) phase noise. As a figure of merit of an RF LO, phase noise determines the OFDM transceiver's sensitivity and bit error rate (BER) performance. Since 5GHz OFDM WLANs are targeting the consumer market, they demand low cost RF transceivers. Because of its potential of integrating a single chip radio, deep submicron CMOS technology is one of the low cost candidates for 5GHz OFDM transceiver chip implementation. However, one of the big challenges for this implementation is to integrate a low phase noise RF VCO. The most difficult phase noise specifications are at low offset frequencies where 1f induced phase noise is going to be the limiting factor due to the increasing of 1f noise in deep submicron MOS devices. Therefore, further phase noise improvement at low offset frequencies requires a fundamental understanding of the 1f noise upconversion mechanism, a better 1f induced phase noise model, systematic low phase noise design methodologies, and innovative circuit techniques. In this thesis, analytical 1f induced phase noise models for CMOS Colpitts and differential VCOs are derived. The derived analytical models physically relate the phase noise to the nonlinear components within a VCO. With these models, the nonlinear behavior of 1f noise upconversion can be analyzed. As a result, the guidelines for low phase noise design and a low frequency feedback technique for 1f induced phase noise reduction are also developed and applied to 5GHz integrated CMOS VCO designs. |
