Design of a wideband quadrature continuous-time delta-sigma ADC

Delta-sigma (DeltaSigma) modulation is a popular technique for making high resolution analog to digital and digital to analog converters (ADC and DAC). This thesis outlines a design procedure for a low power, wide bandwidth, 4th order continuous-time complex bandpass DeltaSigma ADC. System level simulations of the modulator are used to examine the behavior of the modulator in presence of moderate circuit imperfections. The modulator was designed and fabricated in TSMC's 0.18mum CMOS technology. The ADC achieves 68.8dB SNDR in a 23MHz signal bandwidth while consuming 42.6mW from a 1.8V supply. The core area of the IC is 0.95mm2. This work demonstrates the feasibility of implementing a high-resolution high-speed DeltaSigma ADC suitable for a low-IF receiver in deep sub-micron technology using low-gain opamps.