| Bit-serial systems can be attractive alternatives to bit-parallel systems in the signal processing domain, due to the inherent small size, local connectivity, and constant routing density. However, static-timed bit-serial systems are perceived to be difficult to design, as detailed knowledge of bit-serial arithmetic and timing is required, and static delays needs to be inserted to synchronize the data bit streams. This thesis explores a new concept in bit-serial systems, called self-timed bit-serial. Instead of using static delays to adjust timing, a self-timed bit-serial system adapts to its system structure dynamically during run-time. Advantages of such a system include shortened design time, variable word length, and the possibility of run-time reconfiguration. Two applications (floating point addition and speech synthesis) have been implemented and tested on a Xilinx VirtexE FPGA using a self-timed bit-serial architecture. |
