| Over the past 30 years aggressive technology scaling and innovative design techniques have led to the design of high-performance microprocessors that operate at on-chip clock frequencies of more than 3GHz and have 100 million or more transistors. The projections from ITRS 2003 indicate that this trend will continue into the next decade resulting in the integration of over a billion transistors and on-chip clock frequency exceeding 10GHz by the year 2010. However, such aggressive technology scaling is not without its challenges. Some of the most important problems faced by high-performance logic design and test engineers are related to the high power demand, ensuring adequate noise margin and testability. In this thesis we address some of these issues in the context of bulk CMOS based logic and datapath designs.; During the course of this research work, a 32-bit, high performance ALU was designed with circuit level design modifications to ensure its low power operation. In particular, the critical and non-critical units of the ALU were identified and a dual supply design scheme was adopted in-order to minimize both switching and leakage power consumption during the active and standby modes of operation. In addition, a latch (flip-flop) scheme was developed that can support a reduced swing clocking scheme and interface signals between the different power supply domains without consuming additional static power. We also used a swing-restored CPL (SRCPL) based design approach for the non-critical logic and shifter units to lower the overall capacitance and data buffer sizes to reduce overall power (energy). Our results indicate that by using this strategy, it is possible to reduce the operating power by up to 24%.; As the technology is scaled, the transistor leakage current increases exponentially and causes noise margin degradation in digital circuits. Wide-OR domino logic circuits are used extensively in the design of ALU front-ends and register file (RFs). Such circuits are known to be especially susceptible to leakage induced logic upsets in scaled CMOS technologies. In this work we investigated several different circuit level schemes that have already been proposed and compared their effectiveness in improving circuit robustness. In particular, we considered schemes such as reverse body bias, channel length modulation, pseudo-static techniques, conditional keepers and forward body bias. (Abstract shortened by UMI.)... |
