| In microelectromechanical system (MEMS) applications, it is advantageous to have electronic circuitry as near the sensor or actuator as possible. To integrate MEMS devices with electronics on the same wafer, one must consider the typically different processes used to make electronics and MEMS. Having MEMS and electronics on the same wafer often leads to a compromise in performance of either or both systems and introduces the complexity of combining both fabrication processes. An excellent way of avoiding this compromise is to fabricate the optimum MEMS devices and electronics on separate wafers. Then, through-wafer interconnects (vias) with minimum resistances and capacitances are used to connect the MEMS devices on the front side of a wafer to bond pads on the back side of a wafer. The back side of the MEMS wafer can then be flip-chip bonded to the electronics wafer. Applications for this method include infrared (IR) focal plane arrays, spatial light modulators (SLM) of adaptive optics, and three-dimensional ultrasound imaging. The through-wafer interconnect can be modeled as a parallel capacitance and a series resistance. To reduce the parasitic effect of the interconnect, both the capacitance and resistance should be minimal. A technology for high density and low parasitic capacitance electrical through-wafer interconnects is presented here. With this technology, vertical through-wafer interconnects with high aspect ratios, connect an array of sensors or actuators on the front side to flip-chip bond pads on the back side. Minimal parasitic interconnect capacitance is achieved by forming a reverse-biased pn junction diode or metal insulator semiconductor (MIS) junction between the interconnect and substrate. Through-wafer vias for both SOI wafer bonded and surface micromachined MEMS devices are demonstrated. The interconnects described in this thesis provide an elegant means of connecting a transducer array to the electronics of an ASIC, fanout chip, or printed circuit board (PCB). |
