Research On Key Process Of MEMS Wafer-Level Vacuum Packaging

The commercial potentials of micro-electro-mechanical systems (MEMS) wafer-levelvacuum packaging with advantages of small-size and low cost has become obvious, asMEMS based on harmonic structures show brilliant operating experience and perfectperformance in consumer electronics products and high-speed wireless network field.Wafer-level vacuum packaging could be fabricated by the process flows based on waferbonding or sacrificial layer. Pirani meter is used to measure actual pressure in vacuum cavity.Getter and buffer cavity structure are applied to extend packaging life. This paper conducted astudy and related process experiments to implement these micro structures, and obtained thefollowing results.It proposed a kind of vacuum package architecture and its process flow based on thewafer bonding process. The architecture includes through silicon via (TSV), getter, buffercavity and Pirani meter. This process flow was verified by experiments.It obtained the recipes of etching process of TSV by deep reactive ion etch (DRIE) andfilling process without defects by electroplating of double-sided and bottom-up platingmethods. In double-sided method the copper layer generated strong stress and damaged thewafer. Helium mass spectrometer proved that the TSV implemented through bottom-upmethod was hermetic.It was proved that the membrane of Si3N4deposited by low-pressure chemical vapordeposition (LPCVD) kept completely after wet etch in KOH solution and satisfied mechanicalrequirement as supporting membrane. But the membrane of Si3N4deposited by plasmaenhanced chemical vapor deposition (PECVD) and the membrane of SiO2deposited bythermal oxidation deposition cannot meet the requirement. The membranes of Ti and Pt,which deposited by sputter, stripped off in a long-time wet etching by KOH solution. It shouldchange materials or add protective membrane to remain the metal membranes.It proved that the Zr-V-Fe getter could be deposited in cap bottom by lithography-sputter–stripping process flow, and the getter performed well after the process. Wet etchingprocess can fabricate the cap wafer, ordinary or with buffer cavity structure. When the widthof bonding ring is greater than400μm and the depth of etch is less than100μm, the convex corners etch cannot lead to failure.Due to the limit of equipment and conditions in the bottom-up method of TSV filling,the copper particles resulted from the protective photoresist with defect. The protuberantpillars resulted from uniform electroplating. These two faults failed the gold silicon eutecticbonding process and broke silicon wafer.