The design, layout, and characterization of VLSI optoelectronic chips for free-space optical interconnects

The design and testing of very-large-scale-integrated optoelectronic (VLSI-OE) microchips will be described in the context of a free-space optical backplane system. The optical backplane has the potential for providing an enormous amount of bandwidth for telecommunication switching systems and massively parallel computing machines. A free-space optical backplane uses optical design techniques to relay beams of light from the surface of one microchip to the surface of another. By using light to interconnect microchips, the problems associated with high-speed electronic interconnects are avoided. By exploiting the 2-dimensional surface area of the microchips, large numbers of parallel optical interconnections are possible using minute optoelectronic devices patterned on the surface of the chips. By using appropriate optical designs and microchip layouts, massively parallel high-bandwidth interconnects can be implemented within a volume comparable with standard electronic interconnects such as buses and backplanes.; This thesis will begin by describing a specific VLSI-OE chip architecture as well as two free-space optical designs used to interconnect VLSI-OE chips. Details of the design and layout of four separate VLSI-OE chips will then be given and the results of optical and electrical testing of these chips will follow. Finally, the topic of global synchronization will then be considered. Synchronization among many VLSI-OE chips in a multiple-node system requires special attention. A novel approach of providing synchronized clock signals to a multitude of distance points will be discussed.