Packet switched scalable on-chip interconnection architecture design and implementation for Networks-on-Chip

System-on-chip (SoC) design in the billion-transistor era will involve the integration of numerous heterogeneous semiconductor intellectual property (IP) blocks. As a greater number of IP blocks are integrated onto a single chip, a Network-on-Chip (NoC) is emerging as a new design paradigm to overcome the limitations of bus-based communication infrastructure in terms of flexible scalability, higher throughput demand, IP reuse, quality-of-service, and low power.; This thesis presents the design and implementation of a novel packet switched on-chip interconnection architecture for an NoC platform, and also shows promising possibility as a future on-chip interconnection methodology to overcome the bottleneck of today's bus-based SoC designs.; A CDMA NoC architecture that is based on proposed novel on-chip CDMA modulation and demodulation algorithms were implemented and synthesized for ASIC and FPGA platforms. A scalable star network topology that allows a hierarchical, larger switching platform using a central CDMA switch is presented with the implemented architectures. Furthermore, two multimedia applications, 16-point FFT and MPEG-4, have been implemented on the CDMA NoC platform and several performance metrics are determined.; As an extension of dual round robin matching (DRRM) scheduling, a CDMA NoC switch oriented novel scheduling algorithm, called concentric circles dual round robin matching (CC-DRRM), is presented. It allows variable length of codewords to be used in the CDMA switch.; A new design platform that combines the advantages of on-chip switch oriented NoC and GALS with an asynchronous FIFO buffer is presented. Two switch-based GALS NoC models synthesized with an ASIC library were simulated and compared under two platforms with three mixed-clock test scenarios for functional verification and performance analysis.; An on-chip network interface unit architecture that utilizes a Gray code based packet reordering methodology for the purpose of low latency packet processing is presented. The simulation results verify the functionality of the architecture and the reduced latency compared to a conventional packet reordering scheme.; A novel directory-cache embedded switch architecture (DCOS) with distributed shared cache and distributed shared memory is presented. Simulation results show that both cache-to-cache transfer time and execution time of the DCOS scheme are substantially reduced compared to the multiprocessor distributed shared memory system in which switch caches are not embedded.