| This thesis describes the design and measurement of two asynchronous self-timed systems fabricated in a TSMC 0.25 mum CMOS technology. Both designs focus on digital signal processing applications and on achieving power-efficient computation by leveraging the unique characteristics of self-timed systems.;The first design trades off power and performance through dynamic adjustment of the supply voltage. As there is no global clock, halting the system and reestablishing the clock signal is not required to dynamically adjust the supply voltage. In fact, the system continues to operate during supply voltage transients. Combined with an on-chip power management system including on-chip de-dc conversion, the supply voltage is adjusted to just meet software-specified performance requirements. Measurement results demonstrate that the system functions across a supply range from 2.5 V to 650 mV, operating at 770 MHz and 47.5 MHz and dissipating 195 mW and 850 muW at these supply voltage extremes, respectively.;In the second chip, a continuous-time programmable digital FIR filter is designed to process an audio signal in a continuous-time, discrete-amplitude manner. The filter combines an asynchronous ADC, an asynchronous digital processing block, and an asynchronous DAC. The asynchronous ADC in the system generates a "sample" from the incoming signal when the signal crosses a quantization level. The dynamically varying "sample rate" that results leads to dynamic power dissipation in the digital filter that is directly proportional to the incoming signal bandwidth. In addition, as there is no sampling, aliasing is eliminated and in-band quantization error is reduced. Measurement results demonstrate that power dissipation scales with the incoming signal frequency (278.0 mW at 22 kHz and 42.2 mW at 1 kHz). An output spectrum is generated that is characterized only by harmonic distortion. |
