Design and implementation of mobilityfirst router on the NetFPGA platform

We present the hardware prototype design and evaluation of routers in MobilityFirst, a Future Internet Architecture. We chose NetFPGA 1G platform to implement the router. The main task of the router is to perform lookup on MobilityFirst packets which has a two-level addressing scheme (GUID and NA), each level with flat address space. We have designed the MF router to get maximum performance for flow based routing. The forwarding information base of the router has been spread out in Binary CAMs, Block RAMs and external SRAMs which can be updated online. We have achieved a throughput as high as 982Mbps per port (in Gigabit Ethernet). We have provided a way for the router to send updates for missed addresses which allows the host controller to keep a close watch on the network traffic and update the forwarding information base, online. We allow host controller to cache GNRS lookups in the MF router to allow automatic flow based NA binding to be done at line-speeds. Our router buffers the packets if they fail lookups until the forwarding information base is updated and the lookup succeeds. This prototype enables us to analyze the performance bottleneck of MobilityFirst Architecture so that we could continue to improve the architecture and evaluate the performance simultaneously.