Power and leakage minimization for digital ICs

This work targets power minimization in digital integrated circuits (ICs). A globally optimal Lagrangian relaxation based algorithm was developed that robustly minimizes the total active area (the sum of all transistor widths), thus minimizing power, needed for any feasible delay target assuming arbitrary (continuous) cell sizes. An accurate table-lookup delay model was developed from the pre-characterized industrial standard cell library data by making a formal extension to the concept of logical effort which enables optimization of nMOS and pMOS sizes of a cell separately. Then, a new delay-bounded dynamic programming based algorithm was developed that maps the continuous sizes to the discrete sizes available in the standard cell library which achieves active area versus delay results close to the continuous sizing results. Parallelism was incorporated into the algorithm to enhance efficiency by leveraging multi-core processors. Next, a new threshold voltage (VT) selection algorithm was developed that minimizes leakage power while strictly preserving the delay constraint. A key aspect of the approach is a slack-leakage cost function that is globally aware of the entire circuit. The lowest cost cell is swapped to the next highest available VT, as long as the delay is not increased. The procedure iterates until no cell can feasibly be swapped to a higher VT. Finally, a new power optimization flow was presented utilizing separate synthesis and physical cell libraries. The physical library consists of the most power efficient cells whereas the synthesis library includes additional complex cells, which are compound compositions of cells from the physical library. After using state-of-the-art commercial synthesis, the application of the new cell size selection tool resulted in a 36% reduction (on average) in active area. The application of the new VT selection algorithm combined with the near optimal cell size selection tool demonstrated a leakage power reduction of 70% (on average) for single-VT synthesis and 37% (on average) for multi-VT synthesis of industrial designs. The dual library approach resulted in a 13% reduction in active area for the same delay compared to a 40nm industrial library. All the algorithms are efficient, with an ability to handle large commercial designs.