Proposal for a 3.3v/5v low leakage high temperature digital cell library using stacked transistors

Scope and method of study. The objective of this research is to propose a method for developing a low leakage digital cell library capable of performing at extreme temperatures of up to 275°C. The leakage current at extreme temperatures is a dominant factor and plays an important role in determining the circuit performance. A method of stacking low threshold voltage NMOS (NL) transistors over regular threshold voltage NMOS (RN) transistors has proven to reduce the leakage currents at extreme temperatures without much area penalty and loss in performance.; Findings and conclusions. The stacked NMOS transistors were fabricated and leakage data was measured on silicon. The 1.3um (Length: RN=0.8um, NL=0.5um) stacked NMOS device at 3.3 Volts supply voltage and 1.6um (Length: RN=0.8um, NL=0.85um) stacked NMOS device at 5 Volts supply voltage, had Ion/Ioff ratios of 2566 and 1114 respectively at 225°C. The 1.3um and 1.6um length stacked NMOS transistors exhibited 34X and 8X improvement in Ion/Ioff ratios over regular threshold NMOS transistors. The Ioff currents for the 1.3um and 1.6um length stacked devices were 31nA and 81nA respectively at 225°C. The 1.3um length stacked NMOS device at 3.3 Volts supply voltage and 1.6um length stacked NMOS device at 5 Volts supply voltage, had Ion/Ioff ratios of 984 and 724 respectively at 275°C. The 1.3um and 1.6um length stacked NMOS transistors exhibited 22X and 6X improvement in Ion/Ioff ratios over regular threshold NMOS transistors. The Ioff currents for the 1.3um and 1.6um length stacked devices were 76nA and 117nA respectively at 275°C. Three basic combinational gates - Inverter, 3-input NAND and 3-input NOR gates with stacked NMOS transistors were tested on silicon for their Voltage Transfer Characteristic curves and these exhibited very little shift in the switching thresholds at temperatures of 275°C compared to identically sized regular NMOS combinational gates.