A model of emission characterization during the course of chip manufacturing

The semiconductor industry is changing rapidly. Wafer size is increasing to 300 mm. Copper is replacing aluminum as interconnect metal. These new technologies may cause the increase of air emission. In proactive fashion, the semiconductor industry has set an environmental performance goal for its processes.; This thesis presents a model of consumption and emission for major modules: shallow trench isolation, gate, and two interconnect modules (standard and dual damascene). A model of chemical consumption and emissions is built, based upon the contribution of each module in chip process. Overall, 80 percent of the emission is from the CVD and 20 percent from the etch processes, also it is found that a higher clean gas used compared to process gas. A reduction of 90 percent PFC emissions has been demonstrated. A destruction of PFC introduces an increase in HAPs emission. Finally the change to Cu/Low k dual damascene increases the VOC emission.