Variation-aware computer-aided design techniques for VLSI digital circuits

The escalating impact of environmental and process variations on the performance of current and future technology VLSI circuits, necessitates the use of circuit design techniques that can account for these uncertainties.; From a circuit design perspective, the variations may be classified as controllable or uncontrollable in nature. Controllable variations are a class of variations that can be directly reduced or controlled by circuit design techniques that specifically target these types of variation. The variations that are uncontrollable in nature are those for which a circuit design cannot exercise any direct influence. Although uncontrollable variations cannot be directly reduced, their impact on the circuit performance can be controlled by robust circuit design techniques. This thesis presents variation-aware design automation techniques, accounting for both controllable and uncontrollable types of variations, by focusing on three important issues in digital circuit design: power grid design, gate sizing, and timing analysis.; The first part of the thesis addresses the problem of mitigating the controllable variations in the operating environment of a digital circuit, manifested in the form of voltage drop on the power supply network of wires. To control the voltage variations, two topology optimization heuristics for the design of power ground networks have been proposed. These power grid design techniques present a locally regular, globally irregular power grid topology. In the next part of the thesis, we focus on the problem of improving the timing yield of a digital circuit by performing gate sizing in the presence of uncontrollable manufacturing process variations. Through our formulation, we provide a novel worst-casing solution that reduces the pessimism involved in worst-casing by incorporating the effects of spatial correlations of circuit parameters in the optimization procedure. The last part of the thesis explores the problem of performing circuit timing analysis in the face of randomly varying process parameters. A statistical static timing analysis (SSTA) technique, which incorporates correlated parameters, both Gaussian and non-Gaussian, is developed to predict the probability distribution of the circuit delay. The proposed technique is the first scalable SSTA method, which can include correlated non-Gaussian parameters of variation in the SSTA framework.