Research On PMOS FINFET Key Technology

With the rapid development of microelectronics technology, the feature size of thedevice is closer to the physical limits, in order to continue Moore’s Law, peopleconstantly explore new technology, new methods, new materials and new structures, inwhich FINFET structure can effectively suppress the short channel effect, has highercurrent drive capability and good sub-threshold slope, has quasi-planar structure,compatible with the existing Si technology, simple manufacturing method and otheradvantages, therefore, the study of the FINFET structure become a hot spot domesticand international.The paper analyzed the physical properties and stress mechanisms of silicongermanium materials, and the structure of SiGe channel device. Expounded thecommonly process methods in the selective epitaxy grown, reaction principle andprocess factors of selective SiGe epitaxial. Studied the structural features of FINFETand the impact of the structure on its performance,proposed bulk silicon junctionisolation FINFET device structure.Analyzed the structure of bulk silicon FINFET and the impact of physicalparameters on its device performance, using device process simulation tools, studiedthe correlation between device performance and FIN angle, FIN height, FIN thicknessin bulk silicon FINFET structure.The simulation results show that, in order to obtaingood sub-threshold characteristics, the thickness of FIN should be thin and the heightof FIN must high enough to suppress SCE; the FIN angle should be close to90degreeto improve the short-channel effects. Based on this, obtained optimized bulk FINFETdevice structure, finally obtained device optimized process flow.Studied the correlation between device performance and germaniumconcentration, SiGe layer thickness and Si cap layer in SiGe channel PMOS FINFETstructure. Obtained the variation of the device sub-threshold characteristics with thegermanium concentration, SiGe layer thickness and the silicon cap thickness. Thesimulation results show that, with the SiGe channel doping concentration increases orthe SiGe layer thickness increases, the sub-threshold characteristics of the devicebecome better; silicon cap layer can effectively improve the interface trap statesbetween the gate dielectric and the SiGe channel, in addition, when the SiGe layerthickness is too large or germanium concentration is too high,it’s easier to producedual-channel. Based on this, proposed optimized SiGe channel PMOS FINFETstructure, finally optimized the process flow, laid the theoretical basis and practicalfoundation for the design and Performance boost of bulk FINFET device.