| This Ph.D thesis describes and reviews the state-of-the-start 4H-SiC power junction field-effect transistors (JFET). The purpose of thesis research includes design and fabrication of TIVJFET and investigations on the improvements on existing processing technologies, targeting simpler, reliable process that improves device performance.;Fabrication results are presented. Among the results is a normally-off 10 kV, 106 mOcm2 TIVJFET with a record-high value for figure of-merit (FOM) (VB2/RSP-ON) of 943 MW/cm2 among all normally-off SiC FETs.;Processing technologies underwent significant improvements. Simpler and more reliable processes were developed, including Bosch dry etching, Ni self-aligned silicide, thick gate-overlay and oxide trench-fill. All new processes were confirmed in test TIVJFET fabrication and results were presented.;A 430V normally-off TIVJFET of very low RSP-ON of 1.6mOcm 2 was achieved using new developed process. This device has a channel resistance is 0.5mOcm2, corresponding to only one third of channel resistance reported in [25]. This RSP-ON is the lowest among all 400V class normally-off SiC FETs reported to date.;A 1568V normally-on TIVJFET was fabricated using new developed processes. RON-SP was 2.0mOcm2 when current gain was over 12000 (VGS=2.5V). And RON-SP was 1.75mOcm 2 when current gain was over 120 (VGS=3V). This R SP_ON is the lowest among all 1500V class normally-on SiC FETs reported to date. Comparing with the device reported in [16], at the same current gain of 100, this RSP_ON corresponded to a 37% reduction. |
