Low-voltage and low-power silicon transceivers and receivers for W-band and D-band applications

This thesis presents the design and implementation of low-voltage low-power transceivers and receivers in SiGe HBT and CMOS technologies which operate above 75 GHz. Circuit topologies capable of 1.8--2.5 V operation in SiGe HBT technology and 1.0--1.2 V operation in CMOS technology are used to obtain significant power reduction over other state-of-the-art silicon transceivers in the same frequency range, without an associated RF performance penalty. Techniques for minimizing the sensitivity of the VCO to temperature and power supply variations are shown, and modifications to an existing simultaneous noise and input impedance matching methodology in W-band LNAs are described. Three static and Miller frequency dividers for W-band operation are compared, and techniques for optimizing their speed and power consumption are proposed and analyzed theoretically as well as experimentally. A system level design methodology for minimum power consumption and maximum range in radar transceivers is also presented, and solutions to two of the key design challenges of integrated transceivers, namely, LO distribution and transmitter-receiver isolation, are described.;The design methodologies and circuit topologies discussed enable the implementation of a single-chip, 2.5 V, 77--85 GHz Doppler radar transceiver for use in the 77--81 GHz automotive band. An 86--96 GHz receiver is also shown. Both are implemented in a 130 nm SiGe HBT technology with 230 GHzfT and 300 GHzfMAX, and achieve record noise figure, gain, and power consumption for W-band SiGe HBT transceivers and receivers operating above 60 GHz. Using the transceiver and receiver, an experimental investigation of biasing techniques for optimum noise performance is presented. Doppler shift and phase noise measurements performed on the 77--85 GHz transceiver prove experimentally that SiGe HBT technology has ample close-in phase noise performance to measure Doppler shifts of as little as 30 Hz, and that range correlation indeed reduces the phase noise seen in the IF spectrum. Future mm-wave imaging applications and single-transistor stacking circuit topologies are explored, resulting in the implementation of a 1.2 V, 140 GHz receiver in 65 nm GP CMOS.