Compiler transformations for automatic generation of VHDL from C for code acceleration on reconfigurable devices

Reconfigurable computers, where one or more FPGAs are attached to a conventional microprocessor, are promising platforms for code acceleration. Despite their advantages, programmability concerns and the lack of efficient design tools/compilers for FPGAs, are preventing the technology's widespread adoption. The traditional compiler technology is microprocessor-based-systems-specific and needs to be customized and augmented to address the programmability issues of reconfigurable platforms. The challenges are several due to the resources and performance-constraints for FPGAs being drastically different than those of microprocessors, and also that compiling for FPGAs requires laying the computation in space by a circuit rather than in time by a sequence of instructions.; ROCCC is an optimizing C-to-VHDL compiler targeting specifically the reconfigurable computer platforms. ROCCC includes several high-level optimizations that parallelize and optimize the source code for minimized area and critical path length and, maximized throughput. This thesis presents ROCCC's high level transformations and their effect on the performance of the generated VHDL output. In this thesis explained are ROCCC's (1) several array access optimizations, which eliminate redundant memory accesses, (2) procedure-level optimizations that achieve circuit area reductions of up to 88% compared to circuit areas generated from unoptimized codes, (3) loop-level optimizations which help improve the throughput by increasing loop-level parallelism, and (4) application-specific transformations that map certain classes of applications uniquely and most efficiently to hardware. Through these transformations, ROCCC generates circuits with very large degrees of parallelism capable of very high computation rates.