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Compiled acceleration of C programs on FPGAs

Posted on:2009-07-30Degree:Ph.DType:Dissertation
University:University of California, RiversideCandidate:Villarreal, Jason RichardFull Text:PDF
GTID:1448390005451203Subject:Computer Science
Abstract/Summary:
The role of Field Programmable Gate Arrays (FPGAs) as hardware accelerators is a possibility, but is hampered by the difficulty in programming FPGAs. Hand coding hardware is cumbersome and error-prone, and high level languages designed for hardware often have specific constructs to handle hardware concepts which are off-putting to designers unfamiliar with their use. The Riverside Optimizing Compiler for Configurable Circuits (ROCCC) addresses these issues by compiling hardware from a specific subset of C, targeting the sections of the C code that will produce the best hardware implementations.;ROCCC has previously been tested on small sections of code and never generated full systems. This dissertation presents the first complete implementation of a real world application with hardware acceleration completely compiled from C. Presented here is the first hardware accelerated system of NAMD, a popular molecular dynamics simulation system. This system is completely generated by ROCCC from C code and provides speedup over the original implementation.;This dissertation also introduces the new and original compiler transformation of pipelined unrolling. Pipelined unrolling exploits pipelined parallelism by unrolling loops with loop-carried dependencies in order to form large pipelines of components and generates hardware accelerators that outperform equivalent software implementations. This optimization allows for the generation of massive amounts of hardware in a very well structured manner from specific C code and is only beneficial when generating hardware. This dissertation shows both the use of pipelined unrolling to get speedup as well as the integration of pipelined unrolling in the ROCCC compiler. Pipelined unrolling is used to generate speedup for two applications, histogram generation and Bloom filters.;Based upon the work presented here, we introduce the next generation hardware compiler, ROCCC 2.0. ROCCC 2.0 provides designers control over the hardware implementation from the bottom up while still creating implementations in C. In addition to the optimizations supported by the original ROCCC, the ROCCC 2.0 compiler is responsible for automatically connecting components and integrating IP blocks described using C with no extensions.
Keywords/Search Tags:ROCCC, Hardware, Pipelined unrolling, Compiler
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