| Recently, the demand for simultaneous global roaming and all in one wireless phones spurred the interest in developing multi-standard transceivers. These transceivers require low power, low cost and highly reliable designs. As a result, fully integrated RF transceivers have become a hot research topic. With the benefit of submicron technologies, GHz circuits can now be realized in standard MOS technologies, which will help achieve a single chip design solution for the front end. However, CMOS has some inherent limitations, which have to be circumvented using system and circuit techniques to achieve acceptable performance.; This thesis deals with the RF front end of the receiver, which is an important part for the fully integrated single-chip solution of RF transceivers. The communication standards considered here are EGSM, PCS1900 and WCDMA. First, possible traditional transceiver architectures are reviewed. Traditional architectures, such as heterodyne receivers, offer excellent trade-off between selectivity and sensitivity. However, they are not suitable for a fully integrated receiver for multi-standard communication. Single homo-dyne receiver architecture, such as Zero IF or Low IF, along can't satisfy the requirements of multi-standard communication. A Zero/Low IF receiver architecture is chosen as the solution to this problem. System requirements of the receiver are discussed. The Noise and linearity requirements for the whole system and each block of system are calculated according to the specific communication standards. In an analog front end, LNA and Mixer are two important parts. Design issues such as input impedance matching and noise optimization of LNA are covered. The LNA has two gain modes to relax its linearity requirements. The flick noise and linearity of mixer are also discussed. All above blocks are designed in TSMC.18 technology. The simulation and experimental results are presented. |
