Static Timing Analysis Methodology And Research For Sign-off Under UDSM Technology

Ultra-Deep Sub-Micron (UDSM) technology posts a serious challenge to the chip designer and EDA tools on the timing signoff accuracy. Timing signoff uncertainty due to in-die process variation, environmental variation, extraction accuracy and timing modeling accuracy become concerns for the timing signoff of UDSM SoC design. Therefore, the timing analysis becomes more and more complicated. Traditional worst/best case timing sign-off methodology can cover the systematic process variation but can not model the in-die variation and environmental variation effects. This traditional STA flow always leads to 2 kinds of result: Designers overestimate the effects of process variations, which imposed additional burden on the design constraints;or underestimate them and cause manufactured chips to fails. Increase in wafer diameter size, progress in the control of semiconductor manufacturing steps and smaller feature sizes have prompted us to accurately model the uncertainty, to achieve real sign-off. In this paper, I'll present a case study of a 0.13μm 20 million gate design on the various UDSM effects on timing signoff accuracy, collect data under each condition, model various uncertainty, remove unnecessary over-constraints, get summary on STA flow aware of OCV. Furthermore, the advanced theory SSTA (Statistical Static Timing Analysis) will be covered, which is a new road to estimate the effects of OCV in timing analysis. The timing analysis experience on NP design together with the research on SSTA is supposed to provide worthful reference to the further VLSI physical design signoff flow and this chip has been taped out on January 2006.