Efficient VLSI architectures for high-speed Ethernet transceivers

This thesis investigates efficient VLSI architectural design aspects of a digital signal processing (DSP) transceiver in high speed multi-pair wireline communication systems, such as 10 Gigabit Ethernet over copper (10GBASE-T), with the goal to reduce the hardware complexity and power consumption of various DSP components while maintaining the speed and performance requirements. The covered topics mainly include efficient far-end crosstalk (FEXT) cancellers, novel multi-input multi-output (MIMO) equalizers combined with Tomlinson-Harashima Precoding (THP), low complexity echo and near-end crosstalk (NEXT) cancellers.;A novel feedforward delayed FEXT canceller in a THP based system is developed to remove FEXT as noise. Unlike conventional techniques on FEXT cancellation, the proposed FEXT canceller can mitigate the non-causal part of FEXT; thus it can achieve better cancellation performance. In addition, a modified design is developed by eliminating the feedback loops in the FEXT cancellers such that the resulting feedforward FEXT canceller is suitable for high speed applications.;FEXT has been found to contain information about the symbols transmitted from remote transmitters and thus MIMO equalization technique is proposed to jointly process ISI and FEXT such that the useful information in FEXT can be utilized. It is shown that the proposed architecture overcomes the limitation of the traditional equalization schemes and can achieve a better system performance and lower hardware complexity. A computationally efficient approach for calculating the optimal tap coefficients of MIMO equalizers and cancellers is also proposed to speedup the computation. Furthermore, a practical equalization scheme which combines the MIMO equalization technique and TH precoding technique is proposed for the real application of high speed Ethernet systems. Different from existing work on MIMO equalization, the proposed scheme exactly complies with the current 10GBASE-T standard and can be easily pipelined for high speed implementation. Hardware complexity reduction schemes by utilizing the increased decision point SNR (DP-SNR) are also considered.;Gigabit and multi-gigabit transceivers require very long adaptive filters for echo and NEXT cancellation. Implementation of these filters not only occupies large silicon area but also consumes significant power. This thesis considers the problems of designing cost-efficient echo and NEXT cancellers mainly from two different aspects: one is to reduce the number of taps used in these noise cancellers; the other is to reduce the word-length used to represent data in a VLSI system. First, the sparse characteristics of the echo and NEXT channel impulse responses is exploited to reduce computational cost of adaptive echo and NEXT cancellers. Second, a novel word-length reduction scheme is proposed by replacing the original input to the echo and NEXT cancellers with a finite-level signal, which is then recoded to have shorter word-length. To further reduce the complexity of these cancellers, an improved design is proposed by exploiting the property of the compensation signal. Compared with the traditional design, the proposed echo and NEXT cancellers have exact input and do not suffer from the quantization problem, and thus they are more suitable for VLSI implementation. The design issues of adaptive noise cancellers by using the proposed word-length reduction method are also considered and modified designs of the adaptive cancellers are developed to further reduce the overall hardware cost of echo and NEXT cancellers with acceptable cancellation performance. Finally, the design approach for stable pole-zero modeling of long finite impulse response (FIR) filters is proposed.