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VLSI Architectures For The Key Techniques In MIMO-OFDM Systems

Posted on:2014-06-09Degree:DoctorType:Dissertation
Country:ChinaCandidate:X F LiFull Text:PDF
GTID:1268330398998887Subject:Signal and Information Processing
Abstract/Summary:PDF Full Text Request
As a signal propagates through a wireless channel, it experiences random fuctuationsin time if the transmitter, receiver, or surrounding objects are moving with high speed.Thus, some advanced technologies, such as multi-antennas MIMO system, OFDM anditerative decoding algorithms, are adopted for the high speed wireless communicationsystems to gain the best performance. However, the penalty is the strong requirement oncomputation complexity in the receiver. In the last decade, people spent huge efort onthese algorithm’s VLSI implementation to meet the low cost, low power and maintainingthe acceptable performance.This dissertation focus on the VLSI implementation of MIMO spatial multiplexer de-tection, Turbo decoding and FFT processor in the MIMO-OFDM wireless communicationsystems. Some promising results are presented as follows:1. Targeted to the fast fourier transform for the orthogonal frequency-division multi-plexing technique in3GPP LET standard, this paper proposes a single butterfyVLSI architecture with the strategy to time division multiplexing the hardwarerotation digital calculation unit. Here the traditional multiply operation fortwiddle factor is avoided. With respect to the regular and pipeline circuit archi-tecture, the combination circuits path between registers are well balanced, whichleading to the dynamic voltage and frequency can be applied for the optimizedpower management.2. A novel maximum likelihood-like detection algorithm for the2×2MIMO wirelesscommunication system is proposed for that only the second layer in the searchtree needs to be verifed exhaustively, and then applying the area determinationstrategy to the frst layer to fgure out the hypothesis node and counter-hypothesisnodes without sorting the partial Euclidean distance for each layer, which reducesthe complexity signifcantly. The regular VLSI architecture is designed accordingto the detection algorithm, and fexible parallelism can well control the throughputfor versatile applications.3. A novel forward and backward state metric calculation and the memory managementstrategy is presented for the turbo decoder which adopted the Log-MAP(MaximumA-Posteriori) algorithm. By the way of decimating the forward state metric atfrst and then interpolating during the LLR(Log Likelihood Ratio) computationstage to reduce the state metric memory size, which acquired signifcant power and area beneft with ignorable computation penalty. And the soft in soft outscheduling and control mechanism are also addressed for the supporting of ourproposed optimization architecture.4. A parallel-structured turbo decoder based on the maximum a-posteriori algorithm isdesigned for the3GPP LTE system. Taking advantage of the mathematic propertyof the quadratic permutation polynomial, the address of each interleaver, in theparallel processing structure, is separated into two parts, block address and ofsetaddress in that block. An recursive algorithm is developed to calculate these twoaddresses in a parallel decoder,which leads to the parallelism can be any value,breaking the limitation of the power of2. Based on the developed algorithm arecursive VLSI architecture is presented, which signifcantly simplifes the extrinsicinformation interconnecting networks and avoids the usage of interleaver storagememory in the conventional approach.
Keywords/Search Tags:fast fourier transform (FFT), MIMO spatial multiplexer detection, Tur-bo code, MAP decoding, VLSI
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