Study On Algorithm And VLSI Implementation Of High-Speed QAM Demodulator

A variety of modern modulation/demodulation techniques are seeking stable capability of high-speed rate to satisfy the urgent requirement of vast communication data in the digital era of information. The trend of convergence seems among several communication applications such as the "Three networks in one" of telephone, cable TV and Internet along with the development of digital communications. In order to apply several applications in the same propagation channel, we must improve the bandwidth efficiency to save limited frequency resources and achieve high-speed transmission rate. Therefore the wide-band communication has become one of focuses of academic and industrial research.Due to high bandwidth efficiency and noise resistance, Quadrature Amplitude Modulation (QAM) is used widely in High Definition Television (HDTV) broadcasting, cable modem, VDSL and digital microwave communication etc. Especially for digital cable TV employing QAM signaling can transmit one HDTV or 2-4 SDTV programs in a single 8MHz/6MHz channel.The high performance demodulator is the key to ensure high-speed data transmission rate in QAM communication systems. It is possible to implement a single-chip high-speed QAM demodulator on account of the development of digital communication, microelectronics and integrated circuit (IC) design. The implementation of high-speed QAM demodulator needs both the stable demodulation algorithm and the mapping from algorithm to VLSI architecture followed with the optimal chip design. The study on algorithm and VLSI implementation of high-speed QAM demodulator is the core technique of QAM communication and can improve the competitiveness of our design capability with communication ICs in our country.This dissertation studies both the high-speed QAM demodulator algorithm and its VLSI architecture. All-digital implementation of the improved demodulation algorithm ensure stability and high performance. Circuit design is optimized during the mapping from algorithm to VLSIarchitecture according to area, power and speed.The main contribution of this dissertation can be concluded as following.1. Analyzed the architecture of all-digital QAM demodulator. Study on the four key control loops determining the performance of the demodulator and discuss the mutual effect among these loops during the blind demodulation. System analysis and simulation results give the process of steps during the blind demodulation and the detailed requirement of every step.