| This thesis studies the possibility of building efficient all-silicon pulse-compression nonlinear transmission lines (NLTLs). The theory and history of NLTLs are thoroughly reviewed, and the motivation for this project and possible applications are discussed. Silicon coplanar waveguide (CPW) lines and CMOS varactors, as two key components in NLTLs, are fully researched, and were fabricated using a standard 0.18-mum CMOS process. To reduce the dielectric loss caused by the conductive silicon substrate, a slow-wave transmission line technique was further developed, and silicon slow-wave CPW lines were built. A measured S21 loss of only 0.25 dB/mm at 40 GHz is achieved, with an effective relative permittivity as high as 25. Six different types of varactors based on NMOS transistors were investigated. They were divided into two groups: one has monotonic capacitance-voltage curves, and the other has non-monotonic curves. This study demonstrates that the first group is more suited for single-edge, the other for double-edge pulse-sharpening. The NMOS varactors used in the final NLTL designs were fabricated and on-chip measurements up to 55-GHz were made. NLTL transient simulations based on component measurements show a leading-edge rise time reduction of 75% for single-edge, and 60% for double-edge pulse sharpening. Following the investigation of the components, two types of NLTL circuits were designed and built on two CMOS 0.18-mum chips, one was designed for single-edge, the other for double-edge pulse compression. Large-signal measurements, based on the newly developed X-parameter method, show a significant compression with the second type of NLTL However, because of its large attenuation, only minor compression is obtained with the first type of NLTL. This research successfully demonstrates that it is possible to build pulse-compression NLTLs on low-cost commercial CMOS chips. |
