Conception et realisation d'un outil d'exploration architecturale de la hierarchie de memoire d'un systeme sur puce afin d'optimiser la performance de la plateforme logicielle

As the quantity of transistors per single chip steadily increases due to recent advances in lithography, it becomes possible to integrate a number of complex components on an integrated circuit. In order to maximize the use of these transistors, designers now concentrate on multi-processor systems on chip (MPSoC) on which many processors coexist and work together to produce a fast and efficient system. This increasing number of processors on a single chip thus poses new challenges in term of integrated memory utilization.;Previous works dealing with the performance enhancement of such systems by optimizing the memory hierarchy are numerous. Some works focus on effectively using the local memory while others focus on finding the optimal cache configuration. On the other hand, few works focus on the use and optimization of both the local memory and cache.;A tool, MemoryOptimizer, was thus designed to resolve this gap, by presenting a method of design space exploration of the memory hierarchy of a SoC, by using a combination of local memory and cache memory. In order to provide accurate simulation results, a model of the MicroBlaze processor has been implemented in the SPACE simulation platform. Lastly, an execution-tracing tool has been designed and integrated into the MicroBlaze model to provide the metrics necessary for MemoryOptimizer to analyze the behavior of the program executed on the processor.;With MemoryOptimizer, it is now possible to automatically establish the content and the minimal size of the local memory but also the optimal configurations of the caches. The result of this optimization is a system where a small but memory intensive part of the program is relocated in local memory and where the remaining of the program is stored in external memory and access to this memory is accelerated by cache memories. Moreover, the tool can evaluate the minimal size of the stack and the heap to further reduce the memory footprint.;In order to perform optimally, a program executed by a processor is generally contained in a small memory integrated on the chip and directly connected to this processor. This type of memory is called local memory. Because this memory is limited in a given chip, the presence of multiple processors, every one of them striving to provide the best performance, severely limits the amount of local memory available to each processor. Using the integrated memory to store all these programs becomes impossible and mandates the use of an external memory which is much larger but also much slower than the integrated memory.;MemoryOptimizer can greatly enhance the performance of a system based on an external memory while also reducing the size of the required integrated memory. Thus, it is possible to reduce the size of the integrated memory by a factor of 6 while maintaining the same performance level than the same program completely stored in local memory. More processors can now be integrated in a single chip without compromising the execution speed of the programs. Furthermore, the proposed methodology is not limited only to the MicroBlaze and SPACE but can also be adapted to other processors and simulation platforms.