Digitally assisted linearity calibration techniques for high performance direct conversion receivers

Wireless communications have become ubiquitous and are an integral part of our everyday lives. The user's desire for low power, versatile, multi-standard mobile terminals is driving the need for reconfigurable radio-frequency (RF) interfaces based on direct conversion receivers (DCRs). The functional density increase in advanced nanoscale CMOS technologies is indeed making the integration of multi-standard terminals on a single die possible. However, as CMOS feature sizes scale down, the circuit operating supply voltage needs to be reduced and this leads to very significant design challenges to meet the linearity requirements. In many current solutions, external passive filters are used to achieve the necessary linearity, but they significantly add to the size and cost of the terminal. In a DCR, a very significant distortion is from second-order intermodulation products because of strong out-of-band interferers with amplitude modulation. Second-Order Intermodulation Intercept Point (IIP2) requirements can be as high as 60 dBm in receivers for systems using standards like wideband code-division multiple access (WCDMA). An additional challenge is the strong dependence of the IIP2 performance on random variations in the components occurring during circuit manufacture.;In this thesis, we give a detailed analysis of second-order intermodulation generation mechanisms, review various techniques for IIP2 improvement, and present a high performance direct-conversion receiver with digitally assisted IIP2 calibration. It achieves an IIP2 better than 60 dBm without external RF filters and is very robust against process or environmental variations.;In the first part we explore low-power, low-cost and high performance CMOS front-end circuits for DCR implementations. We present the design and analysis of a single-ended low noise amplifier (LNA) and a double balanced, current-driven passive mixer. The LNA drives an on-chip transformer load that performs single-ended to differential conversion. A detailed comparison in gain, noise, and second and third order linearity performance is presented to motivate the choice of a current-driven passive mixer over an active mixer. The front-end prototype was implemented on a 0.13 mum CMOS process and occupies an active chip area of 1.1 mm2. It achieves 30 dB conversion gain, a low double-side-band (DSB) noise figure (NF) of 3.1 dB, an in-band IIP3 of -12 dBm, and IIP2 better than 39 dBm, while consuming only 12 mW from a 1.5-V power supply.;In the second part we investigate the use of digitally-assisted calibration to further improve the receiver second-order linearity. We demonstrate a robust automatic background self-calibration technique for the current-driven passive mixer structure.;The 1.8-GHz CMOS RF front-end uses digital signal processing to improve analog/RF performance, but with minimal hardware overhead and performance penalties on RF front-end and analog baseband. It achieves an IIP2 better than 60 dBm, has a conversion gain of 38.5 dB, a low DSB NF of 2.6 dB, and an IIP3 of -17.6 dBm. It consumes 15 mA from a 1.5-V supply, and occupies 1.56 mm2 on a 0.13 mum CMOS process. This level of performance allows the elimination of the external filter between the LNA and mixer required in earlier designs.