| With the emergence of chip multi-processors (CMPs) as the popular vehicles for general purpose computing, parallel programming is the key to exploiting the additional transistors available with each new hardware generation. Unfortunately, writing parallel programs is hard and hence, proposals that simplify this task would be useful and timely. This thesis investigates hardware support for two such proposals that promise to enhance programmability---Transactional Memory (TM) and Supervised Memory. While TM is a promising idea, existing TM systems suffer from a self-justifying 'small-transaction' assumption that could restrict their applicability to software. Our first proposal redresses the small-transaction assumption by demonstrating TokenTM, an unbounded hardware TM system that gracefully handles virtualization events while still imposing little performance overhead on the execution of small transactions. Our second proposal, StealthTest, expands the applicability of TM systems to the critical area of software testing.;Over the past decades, an increasing number of proposals call for hardware support of semantically richer 'supervised systems' wherein program data is enhanced with metadata and used to supervise (control and monitor) data accesses. While these systems ease the development of safe and efficient software, existing work is still incomplete and leaves many questions unanswered. The final contribution of this thesis deals with enabling correct and efficient supervised systems. We propose Supervised Memory, a formal model that forms the substrate for many supervised systems. We define two consistency models for supervised memory and propose safe supervision, a program property that eases reasoning about consistency models. |
