| In recent embedded systems architecture, memory represents a major bottleneck in terms of power, performance, etc. While traditionally the processor has been extensively customized to match the application, the memory subsystem has been considered as a black box, relying mainly on technological advances (e.g., faster DRAMS, SRAMs), or simple cache hierarchies to improve power/performance. However, in the memory system there is a substantial inter-dependence between the application access patterns, the memory architecture, and the compiler optimizations, offering tremendous opportunities for hardware (memory architecture) and software (compiler and application) customization. Moreover, while real-life applications contain a large number of memory references to a diverse set of data structures, a significant percentage of all memory accesses in the application are generated from a few instructions in the code, that often exhibit well-known, predictable access patterns. By simultaneously customizing the memory architecture to match the access patterns in the application, while retargeting the compiler optimizations to exploit features of the memory architecture, it is possible to significantly improve the system power, and performance. We present such an approach, where we perform hardware customization of the memory architecture exploring a design space substantially wider than traditionally considered, coupled with memory-aware compiler optimizations to significantly improve the memory system behavior for programmable embedded systems. |
