| Optical interconnects have attracted great interest as data rates continue to increase. When compared with their electrical counterparts, optical interconnects have significant advantages in terms of crosstalk, bandwidth, distance, and latency. Many applications stand to benefit from low-cost, high-speed integrated optical transceivers with single-channel gigabit data rates. As in the case of RF wireless designs, using CMOS technology is of special interest due to the potential of lower cost and higher integration.;The analog frontend is a key component in optical receivers due to its importance in bridging the optical and electrical signal domains. In this work, we present a 10 Gb/s optical receiver frontend designed and fabricated in ST's 90 nm CMOS technology. The receiver contains a transimpedance (pre)amplifier (TIA), and limiting amplifier (LA), and an output buffer (OB). The TIA demonstrates a transimpedance gain of 61.9 dBO and a bandwidth of 7.4 GHz, trading off noise and ISI considerations. The single-ended design utilizes 1.5 mW of power from a 1.0 V supply. The LA demonstrates a voltage gain of 21 dB and a bandwidth extended to 10 GHz using inductive peaking. The differential design utilizes 3.9 mW of power from a 1.0 V supply. Finally, the output buffer is capable of driving large output voltage swings to 50O on-chip terminations. In order to test the receiver, a PCB and testing strategy is co-designed with the chip. Details concerning the various design decisions, tradeoffs, are discussed in this thesis. Experimental results of a fabricated device are presented under ideal and practical system levels, with data rates up to 8.5 Gb/s. |
