| In recent years, as the complexity and operating frequency increase, power dissipation of integration circuits has become a critical concern for many VLSI systems. This is especially true in the portable equipments whose growth rate and computation power requirements are outpacing what battery technology can improve by more than ten times. In addition, power dissipation of microprocessors is increasing exponentially in an effort to increase its performance at best at a linear rate, which is facing a diminishing return from the standpoint of energy efficiency. Therefore, design solutions are urgently needed to address the dilemma between demands of high computation power and portability. This dissertation presents a collection of design techniques and methodologies at circuit, logic, and architectural levels of abstraction to enhance the processor performance per watt. Trade-offs of silicon area, performance, and power for different techniques are explored through various processor subcircuit designs. First, a short-circuit power driven circuit technique is proposed to be applied to the non-speed-critical nets in a circuit in order to reduce overall power dissipation without degrading the performance. Then, low-power design techniques for various static and dynamic logic families are proposed for implementing high-performance and low-power adders. To reduce redundant power dissipation due to spurious transitions in datapath elements, a self-timed architecture and circuit combining the merits of dynamic and static logic families are proposed. Later, in order to address low power control logic, several innovative techniques for high-performance, energy-efficient registers, multiplexers, and finite state machines are presented. On the cache memory, a novel cache architecture and circuits are proposed to improve both performance and power. Towards the end, energy consumption of a complete memory hierarchy is optimized with respect to critical cache parameters for energy-efficient processor designs. |
