| The ever-increasing demand for high-quality ICs has motivated the need for defect-oriented test strategies. Defect-based test (DBT) focuses on analyzing information from the physical design and manufacturing process to improve various aspects of test. DBT therefore requires communication between design, manufacturing, and test engineers. Generally speaking, DBT has the potential to better handle emerging defect types and increased levels of defect sensitivity than conventional SSL-based test. For example, DBT that focuses on bridges generates tests for wires that are physically close (i.e. , likely to bridge), whereas SSL-based test focuses only on sites derived from a logic-level circuit model.;In order to test a design effectively, a fault set is identified and test patterns are generated that target each fault. Traditional test strategies examine a logic-level model of the design to extract a set of SSL faults. DBT strategies, on the other hand, employ defect site identification to derive locations from the design layout where defects are likely to occur. For each potential defect site, a fault is created. However, some defect sites cannot be easily modeled and are therefore typically ignored. Based on the set of unmodeled defects, layout modifications can be made to reduce their likelihood.;As new IC manufacturing processes are introduced, defect-based test (DBT) plays an important role in maintaining successful, high-volume, nanometer IC production. The focus of this thesis is on three specific areas of DBT: defect site identification (DSI), defect modeling, and design for testability (DFT). Since the logic of ICs is exhibiting increased levels of regularity to improve manufacturability, we can exploit regularity to enable more cost-effective test strategies, thus improving product quality. By exploiting regularity, we show how these three areas of DBT can be improved. Although the levels of regularity vary between ASIC, VPGA, and logic-brick designs, the fundamental objective is to avoid replication of information and computational tasks. A VPGA has regular routing layers, so analysis of one section of the layout can be used to derive information for the entire design. Although traditional ASIC designs are not fully regular, a standard-cell library is used, so analysis of a standard cell can be used to derive information for every instance of that cell in the layout. The same is true, of course, for logic-brick designs. Moreover, the micro-regularity and macro-regularity of logic-brick designs can be exploited to ensure that information and computational tasks ( e.g., DSI) are not replicated. In summary, each of these design types employs different levels of regularity, and the regularity can be exploited to improve DBT.;We propose DSI strategies that exploit physical regularity to improve efficiency. By calculating critical area for only a small section of a VPGA layout, computation is significantly reduced. Moreover, by representing a logic-brick layout using a bitmap representation, DSI is performed in linear time with the size of the brick. Since computation time is significantly reduced, comprehensive DSI is performed for bridges and opens for both VPGA and logic-brick designs.;Next, we describe a methodology to create fault models for complex defects that would otherwise be ignored. By mapping layout-level circuit nodes within a standard cell to logic-level signals, accurate fault models can be formulated. Moreover, by examining the circuit structure, the complexity of feedback bridges can be represented as logic-level fault models. We also propose a logic-level design representation that includes layout information important for test. By inserting buffers into a logic-level netlist and encoding wire and buffer names with physical-layout information, the netlist is improved to include specific layout information for each wire at the cost of a larger file size. The locations of wires, vias, bends, fanout, and physical neighborhoods provide information that enables more effective defect modeling.;Finally, based on the set of defects that cause difficulties for test, design strategies can be modified to reduce their likelihood. We create an automated method for improving the testability of logic bricks. We formulate yield, quality, and diagnosis enhancements in a SAT formula to optimize the testability of logic bricks. This includes minimizing critical area, reducing the likelihood of feedback bridges, inter-layer bridges, and opens, and eliminating fault equivalency. |
