Performance analysis of processor cache memory with adaptive line size

General-purpose cache architectures are tuned to behave acceptably well across a variety of different kinds of applications. However, the fixed design and behaviour of conventional cache memories prevents them from being re-configured in the most space and power-efficient way to suit the particular run-time statistics of any particular program. In this thesis, we propose a cache memory with reconfigurable capabilities that dynamically adapts its line size, potentially on every cache miss, according to the changing memory requirements of the present application. The adaptive cache aims to improve system performance in a general-purpose microprocessor. Alternative techniques for dynamic performance-oriented optimization are evaluated and opportunities for adaptive cache memories are proposed. The potential performance benefits of the proposed adaptive cache memories are quantified in simulation experiments using the SPEC CPU 2000 benchmark applications.