Font Size: a A A

Architecture-sensitive database query processing on chip multiprocessors

Posted on:2010-09-29Degree:Ph.DType:Thesis
University:Columbia UniversityCandidate:Cieslewicz, John MichaelFull Text:PDF
GTID:2448390002479565Subject:Computer Science
Abstract/Summary:
Microprocessor design is currently in the midst of a sea change, which will have a significant impact on all computer applications including database management systems, the focus of this thesis. For the past several decades, microprocessor performance has been driven primarily by higher clock rates and the subsequent faster execution of a single stream of instructions (a single thread). Faster chip speeds require more power and produce more heat. A single thread also has difficulty providing enough work to keep a chip busy because applications often have to wait for high-latency operations such as loading data from memory, an operation that becomes more expensive in terms of processor cycles the faster a chip is. For these reasons, processor architects have recently begun to improve processor performance by increasing the degree of on-chip thread-level parallelism rather than the chip speed. The processor designs featuring on-chip parallelism are termed chip multiprocessors and include multi-core and simultaneous multithreading processors, both of which are examined in this thesis.;The move toward on-chip parallelism has important implications for computer applications. Database management systems are a core computer application used across disciplines within computer science and in almost every sector of the economy. This means that database performance has a big impact on most data related activities.;This thesis examines the performance of several core database operations on different chip multiprocessor architectures. Performance challenges are identified and architecture-sensitive algorithms designed specifically for chip multiprocessors are proposed and verified. Three core challenges impact database performance on chip multiprocessors: (1) identifying sufficient parallelism with database operations to take advantage of on-chip parallelism, (2) managing shared on-chip resources including memory cache, memory bandwidth, and execution units, and (3) balancing the aforementioned resource sharing with inter-thread communication overhead.;The first part of this thesis examines the use of simultaneous multithreading technology to help overcome performance bottlenecks due to high memory latency in common database join algorithms Then a highly parallel supercomputer is used to demonstrate the benefits of massively parallel architectures for data processing tasks. Finally, the last sections examine core database operations on a commodity chip multiprocessor with the highest currently available degree of on-chip parallelism. Chip multiprocessors are shown to have significant benefits for database performance, but achieving optimal performance requires database algorithms to be crafted with on-chip parallelism as a design parameter from the start.
Keywords/Search Tags:Database, Chip, Performance, Computer
Related items