| The widespread use of multi-core processors has dramatically increased the demands on high bandwidth and large capacity from memory systems. Memory subsystems are becoming performance bottleneck, power and thermal hot spot of contemporary multi-core computing system designs. The power consumption of multi-GB DDR3 memory system can exceed that of the processors for memory-intensive workloads. However, there lack comprehensive studies on memory power/performance design trade-offs and their cost-effective optimization techniques.;To address these issues, in this thesis, we firstly did comprehensive evaluation on memory system performance and power design trade-offs with a large design space and varied multicore workloads. Secondly, with insights and understanding of evaluation study, we proposed a novel mini-rank architecture for significant power saving with limited performance penalty. Thirdly, we further proposed decoupled DRAM architecture for memory system performance, power and cost optimization. Our result shows significant performance, cost and/or power benefits. Both our proposed designs are the latest and representative studies in the recent development on decoupled memory organization. The integration of decoupled DIMM and mini-rank will yield a memory system of both high bandwidth and good power efficiency, and they may together have a long-term impact on future memory system designs. |
