Supply Voltage Minimization with Yield Awareness for Nanoscale SRAMs

Since Static Random Access Memory (SRAM) continues to be the largest component in many embedded digital systems or System-on-Chips (SoCs), its power consumption dominates the overall power of the system, especially in standby mode, and low voltage operations are highly demanded for power reduction. SRAM minimum supply voltage (Vmin) is determined by the lowest acceptable functional yield in the presence of variation. In this thesis, the impact of local and global variation on SRAM Vmin is addressed. New statistical and adaptive design methods are presented to achieve aggressive power reduction by lowering supply voltage to the point near the true SRAM Vmin for the required yield.;Local variation causes randomness in the Vmin of cells on the same array. The tail of the cell Vmin distribution determines the minimum supply voltage for the whole array. For large SRAMs, this tail event occurs once out of millions of samples, and thus standard Monte Carlo (MC) method becomes intolerably expensive. We propose a fast and accurate method for Vmin and yield estimation based on the sensitivity of static noise margin to the supply voltage. It offers comparable accuracy and a significant speed-up (> 104x) over standard MC for tails within 5sigma. It also shows an excellent agreement with two generic fast MC methods for the tail region beyond 5sigma, but with less complexity and smaller estimate variance.;SRAM Vmin also shifts with global variation. The conventional worst case approach overprotects circuit for better conditions, thereby limiting power savings. A new closed-loop standby voltage scaling system is proposed based on canary replica cells, which track global changes so that supply voltage can be adapted to achieve more power savings while maintaining data retention. Measurements from a 90nm test chip demonstrate the function of the canary system. Improvements on canary cells and incorporation of a built-in self-test block enhance the efficiency of the system for more advanced CMOS technologies. Measurements from a 45nm test chip and simulations with predictive technology models down to 22nm demonstrate that the canary-based adaptive approach promises to provide substantial standby power savings in sub-45nm nodes.