| International Technology Roadmap for Semiconductors (ITRS) predicts that CMOS devices will reach their limits in 2022. Consequently, new devices and more efficient technologies are required. In this context, many efforts have been made to extend or replace conventional, CMOS devices. Some devices based on Field Effect Transistor (FET) nanotechnology such as the Dual Gate Carbon NanoTube FET (DG-CNTFET), the Nano Wire FET (NWFET) or the Grapheme FET (GFET) are promising candidates to replace CMOS devices. They lead to define new paradigm of non-conventional architectures (so called nano-component architecture). Nano-component architectures have three main characteristics: (i) The logic cells are dynamically reconfigurable. This characteristic allows performing pipeline on several different functions; (ii) The granularity is ultra-fine (at most 2-bit operation). This characteristic implies to take into consideration scalability to exploit those architectures; (iii) The logic cells are organized with hierarchical structure and connectivity restrictions. In this structure, cells are organized in matrix and the matrices are organized in cluster.;Exploiting those characteristics, nano-architecture are expected, compared to conventional architectures, to reduce the area and the cost and to improve the performance of a broad range of applications. In order to explore the potential of nano-architecture, new CAD tools are required. Those tools must take into account many parameters in nano-architecture definition: the number of cell in matrices, the number of matrices in cluster, the hierarchical structure, the connectivity restrictions, the fine granularity, the high reconfiguration, the pipeline and parallel execution Although many CAD tools defined for conventional architecture have been proposed, they do not take into consideration nano-architecture parameters. This research project aims to explore the system-level potential for nano-architectures; more specifically the aim is to define a mapping model that enables: (i) An automatic application partitioning and mapping for nano-architecture; (ii) The exploration of the design space defined by the nano-architecture parameters; (iii) The optimization of several metrics: the computation speed, the communication cost, the reconfiguration cost and the number of non-used logical cells. |
