| A second generation design and evaluation tool, Rensselaer Interconnect Performance Estimator (RIPE 4.1), has been developed and implemented based on an earlier work (RIPE 3.0) by Geuskens. The enhancements made include new and improved models for crosstalk, wireability, and on-chip cache access-time. The development of these model enhancements follow an approach of critically reviewing available models, benchmarking these with current processors, and finally fixing these for improved results. The new crosstalk model in RIPE 4.1 modifies the model from Nakagawa et al. of Hewlett-Packard to account for non-zero load capacitances and is shown to track SPICE results within 8%. This replaces the older RIPE 3.x crosstalk model based on Sakurai which severely overestimates peak crosstalk voltages by as much as 93% for M4 wires on Intel's Deschutes processor. The new wireability model allows for the automatic design of wiring strategies subject to a processor cycle-time constraint. Previous versions of RIPE (i.e., RIPE 3.0 and before) operate only in a performance analysis mode where, given a wiring strategy as input, the user can check whether the target cycle-time is met. This new wireability model is shown to excellently track wiring requirements for several Intel microprocessors. Finally, a cache-access time model is implemented in RIPE 4.1 to account for the impact of on-chip cache memories on the processor cycle-time. Prior to this version, RIPE makes an implicit assumption that the critical path is only in the logic subsystem.; This thesis also shows the use of RIPE 4.1 to provide wiring strategy requirements for projected technology generations. In particular, the impact of using repeaters, different wire materials (e.g., Cu versus Al, SiO 2 versus Low-K, including K = 1), and alternative 3D wiring for long wires are investigated. It is found that designing multi-GHz processors require a combination of these techniques. Finally, the effects of process-induced linewidth variations on clock frequency, yield, signal integrity, and electromigration are explored. Of these constraints, it is shown that crosstalk is the main limiter for current technologies. |
