Research On Binary Convolutional Neural Network And Its FPGA Implementation

At present,the existing convolutional neural network has complicated structure and bases on huge dataset,so it has difficulties in meeting the requirement of computing performance and limitation of energy consumption requested by some practical applications or computing platforms.We studied the binary algorithm based on ARM+ FPGA platform and designed a binary neural network aiming at these applications or platforms.This network reduces the demand for data storage units and simplifies the computational complexity.First of all,someoptimizations on FPGA have made in this paper,which were matrix algorithm optimization.data distribution optimization.network mode optimization and so on.Some problems encountered in implementing Bianry Neural Network on FPGA were analyzed,and practical solutions were proposed.According to the operation mode of BNN,a parallel pipeline processing method was designed.The inference process of BNN network is divided into three parts,including input module,convolution layer module and full connection layer module.At the same time.the use of C/C++ development mode in the software implementation phase not only reduced the development difficulty of the entire project,but also accelerated the implementation of the algorithm and shortens the development cycle.In the forward inference process of BNN network on ARM+FPGA platform,the convolution multiply-accumulate operation was converted into XNOR logic and pop-count operation.which improved the overall operation efficiency and declined the consumption of energy and resources.Moreover,based on the characteristics of data storage in binary neural network,a new row processing algorithm was put forward to improve the throughput of the network.The results of the final experiment show that the implementation of this paper is superior to the existing FPGA neural network acceleration method in terms of GOPs and efficiency of energy and resource utilizing.