Design Of RFID Integration Processing Circuit Based On CMOS

As an integral processing circuit in the RFID receiver chip structure,it also serves as a core circuit unit commonly used in signal processing.Its technology is improved and integrated with RFID wireless communication,Internet and other information technologies.It is widely used in cargo tracking,access control,highway tolls and other occasions.These application conditions put forward higher requirements on the performance of the integration processing circuit.Therefore,designing an integration processing circuit with lower power consumption and lower temperature coefficient,smaller chip size,and higher power supply voltage rejection ratio is extremely valuable.In the 0.18?m CMOS process,Cadence software design simulation is used to realize an RFID integral with three core circuit modules which has lower power consumption and temperature coefficient,smaller chip size and higher power supply voltage rejection ratio that adapted to high frequency operation in passive RFID.The use of the cascode circuit structure increases the output resistance,weakens the channel modulation,and has an important effect on the increase of the bandgap reference source power supply rejection ratio;In addition,an op amp module with a linear regulator device and a continuous-time common-mode feedback network combined with a differential input-output structure can more efficiently ensure the smoothness of the output common-mode level.After designed and simulated by software,the circuit is operated at a power supply voltage of 1.8V.For the integral processing of 10MHz amplitude and voltage 100mV sine and square wave signals,the temperature coefficient of the bandgap reference voltage source is 2.331ppm/°C.The linear adjustment rate of the circuit module is 0.067%,the differential pressure is 345mV;the phase margin of the op amp reaches 78 degrees,the gain is 93dB,the power supply voltage rejection ratio reaches 80dB,the power consumption of the whole circuit is 1.13mW.The simulation indicators meet the expected requirements with 0.138mm~2 layout area and are finally verified by DRC and LVS.