Design Of LDO Stabilized Voltage Supply Circuit Applied To RFID Tag Chip

The rapid development of microelectronics and information technology has promoted the development of mobile portable devices.In order to obtain a better portable experience,electronic devices are gradually developing in the direction of more convenience and lower power consumption.In addition,single-chip integrated multi-function modules have raised various new demands for power management technology.RFID(Radio Frequency Identification)technology,also known as radio frequency identification,is a communication technology that uses radio frequency signals to identify specific objects.This technology has many advantages,it is widely used in the fields of clothing industry,logistics management,electronic payment and other fields.RFID tag chips,as an indispensable part of the technology,have also received much attention.The power of the RFID tag chip has a greater impact on the sensitivity of the tag,and its power management module is particularly important.The power module must have quick response capability.When the load current changes suddenly,the output voltage will have a large overshoot.For digital circuits,if the adjustment is not timely,a logic error may occur.The power design of the tag chip faces many challenges,such as area limitation,conversion efficiency higher than 90%,low leakage current and low quiescent current under low power conversion and so on.LDO(Low Dropout Regulator)circuit is very suitable for power module of RFID tag chip because of its advantages of fast response,low power consumption and simple structure.This thesis designs an LDO regulated power supply circuit applied to the tag chip to meet its response speed,stable output and low power consumption.The main innovation of this paper is to propose a circuit structure based on FVF(Flipped Voltage Follower)dual feedback,which improves the transient response speed of the feedback loop.Second,using a wide swing cascode current mirror structure,a low temperature coefficient bandgap reference is designed.This thesis uses SMIC 0.18 um CMOS technology to simulate and analyze the designed LDO circuit.Selecting a two-stage amplifier among all those operational amps can achieve design requirements under simulation optimization.The gain is 60 d B and the phase margin is 72°,which meets the stability requirements of operational amplifiers.Based on the Widlar structure,the bandgap reference module uses a wide swing cascode current mirror structure to achieve normal operation in a wide voltage range,with a stable output voltage of 1.21 V and a temperature coefficient of6.725ppm/?.In addition,the bandgap reference and the dual feedback circuit structure based on FVF proposed in this paper form a complete LDO circuit.When it is simulated by Cadence software,it turns out that the power supply rejection ration becomes 62.6d B at a frequency of 1k Hz,and the phase margin is 65 °,which reach the design standard for stable circuits.Apart from this,results also show that the transient output overshoot voltage will be less than 3.36 m V,and the recovery time is 2.72 us,and the undershoot voltage is less than 3.45 m V,and the recovery time is 2.75 us,proving that it meets the corresponding index requirements.