Research On Automatic Test Of ONU Chip In FTTx System

Fiber To The x(FTTx)is a new generation of fiber optic access networks used to connect telecom operators and terminal users.The subject is from the terminal of FTTx system.For the development and design project of ONU(Optical Network Unit)chip,the testing of optical network chip is an indispensable important step before the chip streaming.Testing can reduce the hidden trouble in the development of chips,reduce the risk of error in taping out,saving development costs,shorten the development cycle,chip testing has played a crucial role in the realization of optical access communication.In this paper,the ONU chips are applied in various network scenarios of optical access networks,such as EPON,10GEPON,GPON,XGPON business scenarios such as testing,further manual testing is slow,inefficient and error-prone,and considering the features of a large number of repetitive functional tests stored in the optical network chip test work,an automated test system that can efficiently accomplish a large number of test cases in batches is designed.The system establishes the test environment through the actual traffic model and realizes the chip control with the serial port communication technology,realized a scripting language through the method of keyword definition can be used to write the test process,based on the passive optical communication principle EPON,GPON and other communication protocols,developed the test cases in optical access network chip can meet the basic needs,to achieve The Ethernet,VLAN,packet statistics,address aging,CRC checksum automatic testing fimctions.The experimental results show that the test function of automated test system can meet the test requirements of optical access network communication.Compared with the traditional manual test,the efficiency has been improved fundamentally.The system has been put into use in the project.Particularly,in the iteration version,the system can sharply improve the test efficiency in repeatability function points,which allow testers have more time to carry out more complex test cases,to ensure the success rate of the project chip.