Reliability Analysis And Fault-tolerant Design Research Of Digital Circuits

With CMOS technology scaling,chips are becoming more high-integrated.But it also brought some unprecedented problems for semiconductor industries.The reliability of the circuit in deep submicron level has become a strong concern.Designers included reliability as the fourth optimization pillar of Electronic Design Automation(EDA)tools,along with parameter area,power and latency.To improve the reliability,designers can implement redundancy(such as hardware redundancy and information redundancy)structures for the circuits,of which Triple Modular Redundancy(TMR)structures are the most commonly used.However,these technologies will lead to additional circuit overhead including the increase of area and power.How to significantly improve the reliability while minimizing the deterioration of other parameters is the focus of this thesis.We prefer to use partial redundancy:only to protect the most important modules in a circuit.In the gate level design,the significance related to reliability of each logic gate can be obtained by calculating the reliabilities in sequence.However,with the increasing scale of integrated circuits,reliability analysis will consume more computation time and storage space.In this thesis,we use Fault-Injection-Reliability-Evaluation(FIRE)platform,which is a method based on simulation,to obtain the importance information of logic gates,this platform can be integrated into FPGA and chip design process.Compared with the analytical method,the platform also enables the designer to get the approximate ranking of the importance of logic gates more quickly and conveniently.On the other hand,for some digital applications that are involved in human perceptions,the sensory errors make its accuracy of the operation more relaxed,that is,some errors can be accommodated during the operation.The so-called approximation refers to the deliberate sacrifice of accuracy in exchange for a significant improvement in circuit performance.We can convert logic gates or modules that have less impact on the overall reliability of circuit (i.e.unimportant logic gates or modules)to approximate circuit.In this thesis,we propose a novel approximate adder with hybrid structures.The synthesis results show that the approximate adder has significant performance advantages over approximate adders recently proposed in the literature.Finally,we applied it to the DCT/IDCT image transform to verify the practical value of this approximate adder.