Font Size: a A A

Design Of 25Gbps High Speed Ethernet Interface With 1588 Protocol

Posted on:2020-06-06Degree:MasterType:Thesis
Country:ChinaCandidate:Y W ZhangFull Text:PDF
GTID:2428330626950791Subject:Integrated circuit engineering
Abstract/Summary:PDF Full Text Request
With the rapid development of cloud data centers and the increasing demand for high bandwidth by operators,the access network has gradually upgraded from 10 Gbps to 25 Gbps,providing high-density,low-cost and lowpower solutions for server-to-switch connections.With the popularity of 25 Gbps Ethernet,research and design for 25 Gbps Ethernet interfaces is also imperative.This topic studies and analyzes the hardware access control layer(MAC)and physical coding sublayer(PCS)of 25 Gbps high-speed Ethernet interface.Firstly,according to the IEEE802.3by standard protocol,the MAC sublayer and PCS sublayer of the 25 Gbps high-speed Ethernet interface are deeply studied and analyzed,and the MAC sub-layer and PCS sub-layer overall architecture of the 25 Gbps high-speed Ethernet interface are designed.At the same time,the module is divided according to the function of each sub-layer,and the hardware circuit design is performed for each sub-module.To ensure the accuracy of the design clock,1588 high-precision time stamps were added to the design.The key points of this design include the following three points: the first is to implement data flow control function in the MAC sublayer of 25 Gbps high-speed Ethernet interface;the second is to implement Gearbox function in the PCS sublayer of 25 Gbps high-speed Ethernet interface;the third is The 64B/66 B data encoding and decoding function is implemented in the PCS sublayer of the 25 Gbps high speed Ethernet interface.After the design is completed,the project builds a Universal Verification Methodology(UVM)verification platform to verify the design and pass the Field Programmable Gata Array(FPGA)and Spirent network test instrument.Designed for board level testing.The test results show that the design implements the 25 Gbps high-speed Ethernet interface MAC sub-layer and PCS sub-layer functions required in the protocol,and meets the requirements of 25 Gbps when the clock frequency is 390.625 MHz,and the data transmission is long-term.There is no packet loss or wrong packet in the process,which ensures the correctness and stability of the design.This thesis specifically designed a 25 Gbps high-speed Ethernet interface that supports the 1588 protocol function.While implementing the 25 Gbps high-speed Ethernet interface function,it provides a feasible solution for the development of 25 Gbps high-speed Ethernet interface in the field of high-bandwidth data centers.
Keywords/Search Tags:data center, IEEE802.3by, 25Gbps Ethernet Interface, 1588, UVM
PDF Full Text Request
Related items