Design And Implementation Of RTPS Message Parsing And Encryption And Decryption System Based On FPGA

For computationally intensive tasks and computational complex tasks,traditional processing methods are mostly based on CPU implementation.Since the CPU is a general-purpose processor,when dealing with computationally intensive tasks or computing complex tasks,the speed is not particularly fast,and it is difficult to meet today's high-speed and complex network environments.The FPGA can generate different functions of the circuit by configuring different programming data,and the parallelism of the circuit far exceeds the CPU,which greatly improves the processing speed of the program.Therefore,this paper designs a set of RTPS message parsing and AES-256 data encryption and decryption system based on FPGA to improve the processing speed of RTPS message decryption,parsing and encryption.The main contributions of this thesis are concluded as follows:1)Study the AES algorithm and design FPGA-based AES-256 encryption and decryption system.Solved the complex 256-bit key expansion problem in encryption and decryption.The operation of the AES algorithm on the FPGA is implemented,and ensuring the security and execution rate of the algorithm.2)Analyze RTPS messages and design an FPGA-based RTPS message parsing system.Designed three types of analysis methods: A,B,and C,and solved the problem of the analysis of the indefinite length field in the sub-message and the timing constraint between each module.For the first time,the RTPS message is parsed on the FPGA,which speeds up the parsing speed.3)Data transmission between PC and FPGA is realized by PCI-e communication method.Based on the RIFFA framework,the MFC data transceiver control program and FPGA data transceiving and processing program are designed respectively;4)A prototype system is designed and implemented.The system includes the modules of the communication between the PC and the FPGA through PCI-e;data delivery from the PC to the FPGA;task scheduling and exection based on data flag;data display.5)The function test and performance test of the system are carried out.The experimental results show that the FPGA-based RTPS packet decryption,parsing,and encryption data processing system can run normally;When processing AckNack messages,the FPGA runtime is about 13% of the CPU under the same amount of data,and in the same time,the amount of data processed by the FPGA is 1400 times that of the CPU.The system occupies 32% of the LUT,15% of the FF and 35% of the BRAM,and the total power consumption is 0.567 W.